Frip-chip bonding is a method of connecting a silicon chip to a substrate by flipping over the chip so that its top side faces down and connecting the chip via solder bumps provided on the top side of the chip where integrated circuits are created, hereinafter referred to as “circuit side.” An underfill composition fills a space between the silicon chip and the substrate to secure reliability of the connection by preventing cracks in the solder connection. Conventionally, an underfill composition fills the space between the silicon chip and the substrate by capillary action. However, in a large scale semiconductor device where a side length of a silicon die exceeds 10 mm or even 20 mm, a part of the space between the silicon chip and a substrate tends to remain unfilled with an underfill composition. An underfill composition containing lower amount of filler can fill the space more easily, but a cured product of such agent has larger thermal expansion coefficient, causing problems such as peeling at an interface between the cured product of the underfill composition and the chip or the substrate.
In addition, a process of soaking an underfill composition by capillary action requires many steps, increasing manufacturing costs. To solve this problem, Japanese Patent Application Laid-Open No. 04-280443 discloses a so-called non flow underfill method. In this method, an underfill material comprising a flux agent is applied on a surface of the substrate before bonding a chip, and the applied underfill composition is cured simultaneously with soldering a chip to the substrate. By using this method, manufacturing costs can be reduced.
The aforesaid flux agent is a proton donor such as abietic acid which reduces oxidized surface of solder bumps. In the reduction reaction, water is generated which vaporizes during a reflow process and tends to cause voids in the solder connection.
Japanese Patent Application Laid-Open No. 2000-174044 discloses so-called B-stage underfill or wafer-level underfill method in which an underfill composition applied on a silicon wafer is brought into a B-stage and then diced together with the wafer. Japanese Patent Application Laid-Open No. 2003-243449 discloses an improvement of the method in which an underfill layer consists of two layers: one layer comprising a flux used to surround solder bumps and the other layer which comprises filler and is placed on solder joint pads provided on a substrate. A drawback of the method is laborious steps of applying an underfill composition to a wafer and to a substrate, respectively. In addition, solder contact failure may occur due to lack of flux on the pads. Further, the layer comprising the filler has poor transparency, so that the layer degrades visibility of solder bumps when it covers the solder bumps, causing difficulty in positioning of the wafer in dicing and soldering processes. Moreover, the underfill composition comprising flux surrounds the solder bumps, so that voids tend to occur by water vapor as described above.
Japanese Patent Application Laid-Open No. 2005-268704 discloses a method in which an underfill composition is applied in such a thickness that a top of a solder ball protrudes from the applied underfill composition and then is put into a B-stage followed by applying a flux on the top of the solder ball. The method, however, is laborious in that the underfill composition had to be applied to each device package and the flux had to be applied to each device package after the underfill composition is brought into a B-stage. Further, a cured product of the underfill composition may be adversely affected due to a compositional change caused by a possible reaction between the flux and the underfill composition.
Japanese Patent Application Laid-Open No. 2006-229199 discloses a wafer-level underfill method in which a hot-melt type of underfill composition is polished till a top of a solder bump appears and then diced. In the method, however, voids tend to be formed due to curing shrinkage, and fillets surrounding a chip tend to be formed. Moreover, exposed solder tends to be oxidized. This necessitates application of larger amount of commercially available flux which tends to form voids due to a large amount of diluent contained in the flux.